View VL6524_707692.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

VL6524 VS6524
VGA single-chip camera module
Preliminary Data
Features

640H x 480V active pixels 3.6 m pixel size, 1/6 inch optical format RGB Bayer color filter array Integrated 10-bit ADC Integrated digital image processing functions, including defect correction, lens shading correction, demosaicing, sharpening, gamma correction and color space conversion Embedded camera controller for automatic exposure control, automatic white balance control, black level compensation, 50/60 Hz flicker cancellation and flashgun support Up to 30 fps progressive scan, flexible subsampling and cropping modes ITU-R BT.656-4 YUV (YCbCr) 4:2:2 with embedded syncs, RGB 565, RGB 444 or Bayer 10-bit output formats Viewlive feature allows different sizes, formats and reconstruction settings to be applied to alternate frames 8-bit parallel video interface, horizontal and vertical syncs, 24 MHz clock Two-wire serial control interface (I2C) On-chip PLL, 6.5 to 26 MHz clock input Analog power supply, from 2.4V to 3.0V Separate I/O power supply, 1.8V or 2.8V levels 3.3V tolerant I/O for power supply > 2.7V Integrated power management with power switch, automatic power-on reset and powersafe pins Low power consumption, ultra low standby current Dual-element plastic lens, F# 2.8, ~59 DFOV (VS6524)
SmOP
LGA
Description
The VL6524/VS6524 is a general purpose VGA resolution CMOS color digital camera featuring low size and low power consumption. This complete camera module is ready to connect to camera enabled baseband processors, back-end IC devices or PDA engines.

Applications

Mobile phone Videophone Video surveillance Medical Machine Vision Toys PDA Biometry Bar Code Reader Lighting Control

November 2006
Rev 3
1/70
www.st.com
1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
VL6524/VS6524
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 3
Electrical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1 Video pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Microprocessor functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
Operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 5.2 5.3 5.4 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 System clock division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pixel clock (PCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PCLK gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Output frame size control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1.1 6.1.2 Cropping module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Subsampling module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 6.3 6.4
Frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2.1 Horizontal mirror and vertical flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ViewLive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Video pipe setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Output data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 7.2 YUV 4:2:2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 RGB and Bayer data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2.1 Manipulation of RGB data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/70
VL6524/VS6524 7.2.2
Contents Dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Data synchronization methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1 Embedded codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1.1 8.1.2 8.1.3 Prevention of false synchronization codes . . . . . . . . . . . . . . . . . . . . . . . 26 Mode 1(ITU656 compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2
VSYNC and HSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2.1 8.2.2 Horizontal synchronization signal (HSYNC) . . . . . . . . . . . . . . . . . . . . . 29 Vertical synchronization (VSYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.1 9.2 Initial power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Minimum startup command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10
Host communication - IC control interface . . . . . . . . . . . . . . . . . . . . . 32
V2W protocol layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Detailed overview of the message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Start (S) and Stop (P) conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Index space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Types of messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Random location, single data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Current location, single data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Random location, single data read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Multiple location write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Multiple location read stating from the current location . . . . . . . . . . . . . . . . . . . . . 40
11
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Low level control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Device parameters [read only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Mode Status [read only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 RunModeControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Clock manager input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3/70
Contents
VL6524/VS6524 Power management control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Pipe setup bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Pipe setup bank0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Pipe Setup Bank1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 View live control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 White balance control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Exposure control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Exposure status (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Exposure algorithm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flashgun control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flicker frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Defect correction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Sharpening control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Fade to black damper control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Dither control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Output formatter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12
Optical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.1 12.2 Average sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Spectral response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
13.1 13.2 13.3 13.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13.4.1 13.4.2 13.4.3 13.4.4 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Chip enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 IC slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Parallel data interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.5
ESD handling characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
14.1 14.2 SmOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4/70
VL6524/VS6524
Contents
15 16
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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List of tables
VL6524/VS6524
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. VL6524/VS6524 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Subsampled image sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ITU656 embedded synchronization code definition (even frames). . . . . . . . . . . . . . . . . . . 27 ITU656 embedded synchronization code definition (odd frames). . . . . . . . . . . . . . . . . . . . 28 Mode 2 - embedded synchronization code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Low-level control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Device parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Mode status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 RunModeControl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Clock manager input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Power management control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Pipe setup bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Pipe setup bank0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Pipe setup bank1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 View live control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 White balance control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Exposure control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Exposure status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Exposure algorithm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flashgun control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flicker frequency control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Defect correction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Sharpening control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Fade to black damper control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Dither control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Output formatter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Optical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 VS6524 average sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Supply specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Serial interface voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Parallel data interface timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 ESD handling characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 LGA package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 VL6524 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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VL6524/VS6524
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. VL6524/VS6524 simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 State machine at power -up and user mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Frame output format against framerate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VGA 30fps output frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Crop controls (Table 16: Pipe setup bank0 control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Crop 30fps output frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ViewLive frame output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Standard Y Cb Cr data order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Y Cb Cr data swapping options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 RGB and Bayer data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ITU656 frame structure with even codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Mode 2 frame structure (VGA example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 HSYNC timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 VSYNC timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Write message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Read message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Detailed overview of message format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Device addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SDA data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Data acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Internal register index space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Random location, single write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Current location, single read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Random location, single data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Multiple location read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Multiple location read starting from a random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 VS6524 spectral response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Voltage level specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SDA/SCL rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Parallel data output video timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 VS6524Q06J outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 VS6524Q06J socket assembly outline drawing for information only . . . . . . . . . . . . . . . . . 65 VL6524QOMH outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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Overview
VL6524/VS6524
1
1.1
Overview
Description
The VL6524/VS6524 is a VGA resolution CMOS imaging device designed for low power systems. Video data is output from the VS6524 over an 8-bit parallel bus in RGB, YCbCr or bayer formats and is controlled via an IC interface. The VL6524/VS6524 requires an analogue power supply of between 2.4 V to 3.0 V and a digital supply of either 1.8 V or 2.8 V (dependant on interface levels required). An input clock is required in the range 6.5 MHz to 26 MHz. The device contains an embedded video processor and delivers fully color processed images at up to 30 frames per second. The video processor integrates a wide range of image enhancement functions, designed to ensure high image quality, these include:

Automatic exposure control Automatic white balance Lens shading compensation Defect correction algorithms Demosaic (Bayer to RGB conversion) Matrix compensation Sharpening Gamma correction Flicker cancellation
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VL6524/VS6524
Electrical interface
2
Electrical interface
The device has 20 electrical connections as listed in Table 1. The physical orientation of the pins on the device is shown in Figure 36. Table 1.
Pad socket 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VL6524/VS6524 signal description
Pad name GND D02 D03 HSYNC VSYNC D07 D06 D05 D04 CLK GND FSO CE SCL SDA AVDD D01 D00 PCLK VDD I/O PWR OUT OUT OUT OUT OUT OUT OUT OUT IN PWR OUT IN IN I/O PWR OUT OUT OUT PWR Analogue ground Data output D2 Data output D3 Horizontal synchronization output Vertical synchronization output Data output D7 Data output D6 Data output D5 Data output D4 Clock input - 6.5MHz to 26 MHz Digital ground Flash output Chip enable signal active HIGH IC clock input IC data line Analogue supply 2.4 V to 3.0 V Data output D1 Data output D0 Pixel qualification clock Digital supply 1.8 V OR 2.8 V Description
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System architecture
VL6524/VS6524
3
System architecture
The VL6524/VS6524 consists of the following main blocks:

VGA-sized pixel array Video timing generator Video pipe Statistics gathering unit Clock generator Microprocessor
A simplified block diagram is shown in Figure 1. Figure 1.
VL6524/VS6524 simplified block diagram
CLK
Clock generator
IC Interface IC
SDA SCL
CE VDD GND
Reset VREG
Microprocessor
Video timing generator
Statistics Gathering
FSO AVDD VGA Pixel array GND Video pipe VSYNC HSYNC PCLK D[0:7]
3.1
Operation
A video timing generator controls a VGA-sized pixel array to produce raw images at up to 30 frames per second. The analogue pixel information is digitized and passed into the video pipe. The video pipe contains a number of different functions (explained in detail later). At the end of the video pipe data is output to the host system over an 8-bit parallel interface along with qualification signals.
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VL6524/VS6524
System architecture
The whole system is controlled by an embedded microprocessor that is running firmware stored in an internal ROM. The external host communicates with this microprocessor over an IC interface. The microprocessor does not handle the video data itself but is able to control all the functions within the video pipe. Real-time information about the video data is gathered by a statistics engine and is available to the microprocessor. The processor uses this information to perform real-time image control tasks such as automatic exposure control.
3.1.1
Video pipe
The main functions contained within the VL6524/VS6524 video processing pipe are as follows. Gain and offset: This function is used to apply gain and offset to data coming from the sensor array. The required gain and offset values result from the automatic exposure and white balance functions from the microprocessor. Anti-vignette: This function is used to compensate for the radial roll-off in intensity caused by the lens. By default the anti-vignette setting matches the lens used in this module and does not need to be adjusted. Crop: This function allows the user to select an arbitrary Window Of Interest (WOI) from the VGA-sized pixel array. It is fully accessible to the user. Defect correction: This function runs a defect correction filter over the data in order to remove defects from the final output. This function has been optimized to attain the minimum level of defects from the system and does not need to be adjusted. Demosaic: This module performs an interpolation on the Bayer data from the sensor array to produce an RGB image. It also applies an anti-alias filter. Subsampler: This module allows the image to be sub-sampled in the X and Y directions by 2, 3, 4, 5 or 6. Matrix: This function performs a color-space conversion from the sensor RGB data to standard RGB color space. Sharpening: This module increases the high frequency content of the image in order to compensate for the low-pass filtering effects of the previous modules. Gamma: This module applies a programmable gain curve to the output data. It is user adjustable. YUV conversion: This module performs color space conversion from RGB to YUV. It is used to control the contrast and color saturation of the output image as well as the fade to black feature. Dither: This module is used to reduce the contouring effect seen in RGB images with truncated data. Output formatter: This module controls the embedded codes which are inserted into the data stream to allow the host system to synchronize with the output data. It also controls the optional HSYNC and VSYNC output signals.
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System architecture
VL6524/VS6524
3.2
Microprocessor functions
The microprocessor inside the VL6524/VS6524 performs the following tasks: Host communication: handles the IC communication with the host processor. Video pipe configuration: configures the video pipe modules to produce the output required by the host. Automatic exposure control: In normal operation the VL6524/VS6524 determines the appropriate exposure settings for a particular scene and outputs correctly exposed images. Flicker cancellation: The 50/60Hz flicker frequency present in the lighting (due to fluorescent lighting) can be cancelled by the system. Automatic white balance: The microprocessor adjusts the gains applied to the individual color channels in order to achieve a correctly color balanced image. Dark calibration: The microprocessor uses information from special dark lines within the pixel array to apply an offset to the video data and ensure a consistent `black' level. Active noise management: The microprocessor is able to modify certain video pipe functions according to the current exposure settings determined by the automatic exposure controller. The main purpose of this is to improve the noise level in the system under low lighting conditions. Functions which `strength' is reduced under low lighting conditions (e.g. sharpening) are controlled by `dampers'. Functions which `strength' is increased under low lighting conditions are controlled by `promoters'. The fade to black operation is also controlled by the microprocessor
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VL6524/VS6524
Operational modes
4
Operational modes
VL6524/VS6524 has a number of operational modes. The STANDBY mode is entered and exited by driving the hardware CE signal. Transitions between all other modes are initiated by IC transactions from the host system or automatically after time-outs. Figure 2. State machine at power -up and user mode transitions
Supplies turned ON & CE pin LOW Supplies OFF Supplies turned OFF
Power-down
Supplies turned-off State Machine at power-up I2C controlled user mode transitions Standby
CE pin LOW CE pin HIGH
1
STOP mode
Flashgun mode
PAUSE mode
Run mode
Note:
1
It is possible to enter any of the user modes direct from Standby via an I2C command
Power Down/Up: The power down state is entered from all other modes when CE is pulled low or the supplies are removed. During the power-down state (CE = logic 0)

The internal digital supply of the VL6524/VS6524 is shut down by an internal switch mechanism. This method allows a very low power-down current value. The device input / outputs are fail-safe, and consequently can be considered high impedance.
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Operational modes During the power-up sequence (CE = logic 1)

VL6524/VS6524
The digital supplies must be on and stable. The internal digital supply of the VL6524/VS6524 is enabled by an internal switch mechanism. All internal registers are reset to default values by an internal power on reset cell.
Figure 3.
Power up sequence
POWER DOWN standby
VDD (1.8V/2.8V) AVDD (2.8V) CE
t1 t2
t3 CLK SDA SCL t5 Constraints: t1 >= 0ns t2 >= 0ns t3 >= 0ns t4 >= 25ms t5 >= 2ms low level command:enable clocks setup commands t4
STANDBY mode: The VL6524/VS6524 enters STANDBY mode when the CE pin on the device is pulled HIGH. Power consumption is very low, most clocks inside the device are switched off. In this state IC communication is possible when CLK is present and when the microprocessor is enabled by writing the value 0x06 to the MicroEnable register 0xC003 (Table 7). All registers are reset to their default values. The device I/O pins have a very highimpedance.
Note:
On exit from STANDBY mode, the VL6524/VS6524 is in a transient mode called UNINITIALISED, this mode is not a user mode.
STOP mode: This is a low power mode. The analogue section of the VL6524/VS6524 is switched off and all registers are accessed over the IC interface. A run command received in this state automatically sets a transition through the PAUSE state to the run mode. PAUSE mode: In this mode all VL6524/VS6524 clocks are running and all registers are accessible but no data is output from the device. The device is ready to start streaming but is halted. This mode is used to set up the required output format before outputting any data.
Note:
The PowerManagement register bTimeToPowerdown can be adjusted in PAUSE mode but has no effect until the next RUN to PAUSE transition (Table 13).
RUN mode:This is the fully operational mode.
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VL6524/VS6524
Operational modes
ViewLive: this feature allows different sizes, formats and reconstruction settings to be applied to alternate frames of data, while in run mode. FLASHGUN mode: In flashgun mode, the array is configured for use with an external flashgun. A flash is triggered and a single frame of data is output and the device automatically switches to Pause Mode.
Mode transitions
Transitions between operating modes are normally controlled by the host by writing to the Mode control register. Some transitions can occur automatically after a time out. If there is no activity in the PAUSE state then an automatic transition to the STOP state occurs. This functionality is controlled by the Power management control register. Writing 0xFF disables the automatic transition to STOP mode.
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Clock control
VL6524/VS6524
5
5.1
Clock control
Input clock
The VL6524/VS6524 contains an internal PLL allowing it to produce accurate frame rates from a wide range of input clock frequencies. The allowable input range is from 6.5 MHz to 26 MHz. The input clock frequency must be programmed in the uwExtClockFreqNum (MSB), uwExtClockFreqNum (LSB) and bExtClockFreqDen registers (Table 12). To program an input frequency of 6.5 MHz, the numerator can be set to 13 and the denominator to 2. The default input frequency is 12 MHz.
5.2
System clock division
It is possible to set an overall system clock division of 2 in the bEnableGlobalSystemClockDivision register (Table 12). This results in a PCLK of 12MHz and a maximum frame rate of 15fps VGA.
5.3
Pixel clock (PCLK)
All data output from the VL6524/VS6524 is qualified by the PCLK output. The PCLK frequency is 24 MHz (equivalent to a 12 MHz pixel rate as each pixel is represented by 2 bytes of data). For frame rates less than 30 fps the PCLK frequency is not reduced, instead additional interframe lines are added into the output data stream.
Figure 4.
Frame output format against framerate
Frame output 30fps Frame output 15fps
ACTIVE VIDEO 1/30 sec
Interline Blanking
ACTIVE VIDEO
Interline Blanking
Interframe Blanking 1/15 sec
1/30 sec
ACTIVE VIDEO
Interline Blanking
Interframe Blanking
Interframe Blanking
ACTIVE VIDEO 1/30 sec
Interline Blanking
ACTIVE VIDEO
Interline Blanking
1/15 sec
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VL6524/VS6524
Clock control
Similarly when using sub-sampled output modes the PCLK frequency is not reduced but instead pairs of PCLKs are 'dropped', see Section 6.1.2: Subsampling module for details. The PCLK edge used to qualify the output data is fully programmable. It is also possible to program the state of the PCLK line (high or low) for the times when it is inactive.
5.4
PCLK gating
By default the PCLK output from the VL6524/VS6524 is not continuous. The PCLK qualifies all video data (and embedded codes if selected) on each video line and each interframe line but does not qualify the interline blanking data. In non-subsampled modes the PCLK is continuous during the video data output. The operation of the PCLK can be controlled using the bPClkSetup register (Table 29).
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Output frame size control
VL6524/VS6524
6
6.1
Output frame size control
Frame format
An output frame consists of a number of active lines and a number of interframe lines. Each line consists of embedded line codes (if selected), active pixel data and interline blank data. Note that by default the interline blanking data is not qualified by the PCLK and therefore is not captured by the host system. The default 30fps VGA output frame is shown in Figure 5. Figure 5. VGA 30fps output frame
1460 PCLKs
16 interframe blanking lines(0x10/0x80) 1280 PCLKs
553 lines
480 lines ACTIVE VIDEO (640 by 480 pixels)
Line blanking (0x10/0x80)
37 interframe blanking lines (0x10/0x80)
If embedded codes are enabled then 8 additional clocks are required in every line to qualify the codes and 8 fewer interline clock are output leaving the total constant at 1460 clocks per line. By default the PCLK output does not qualify the line blanking data and so each line contains only 1280 clocks (or 1288 if embedded codes are enabled). The values which are output during line and frame blanking are an alternating pattern of 0x10 and 0x80 by default. These values can be changed by writing to the BlankData_MSB and BlankData_LSB registers in the Output formatter control bank.
6.1.1
Cropping module
The VL6524/VS6524 contains a cropping module which can be used to define a window of interest within the full VGA array size. The user can set a start location and the required output size. Figure 6 shows the example with pipe setup bank0.
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VL6524/VS6524 Figure 6.
Output frame size control Crop controls (Table 16: Pipe setup bank0 control)
Sensor array horizontal size = 640
uwCropHStartMSB0 uwCropHStartLSB0
,uwCropVStartMSB0 uwCropVStartLSB0
Sensor array vertical size = 480
Cropped ROI
uwCropVSizeMSB0 uwCropVSizeLSB0
uwCropHSizeMSB0 uwCropHSizeLSB0
FFOV VGA Array
Complete lines which fall outside the window of interest are replaced in the output data frame with lines of blanking data thus the overall frame length is not reduced. The portion of the output line which contains video data is reduced in length to contain only those pixels defined by the window of interest. However the overall line length remains unchanged as the number of interline clocks increases by the same amount. Figure 7. Crop 30fps output frame
1460 PCLKs
Interframe blanking lines 2x CropHsize PCLKs CropVsize Lines (CropHsize by CropVsize pixels)
553 lines
Line blanking
Interframe blanking lines
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Output frame size control
VL6524/VS6524
6.1.2
Subsampling module
The VL6524/VS6524 has a built in sub-sampler which can divide the image by 1, 2, 3, 4, 5, or 6. Using the sub-sampler gives output images with reduced resolution but the same field of view as the full VGA image or the region of interest defined in the cropping module. Table 2 lists the available image sizes. Table 2. Subsampled image sizes
Image format VGA QVGA QQVGA SQCIF Image dimensions 640 by 480 320 by 240 213 by 160 160 by 120 128 by 96 106 by 80
Subsample ratio 1 (default) 2 3 4 5 6
Subsampled images are produced by `dropping' PCLKs so that only certain pixels are qualified in the output data stream. The figure below indicates a portion of the PCLK waveform for VGA and QVGA images. The effect of this is that the time taken to readout one line of the image remains constant in all subsampled modes - it is just the number of clocks that changes. Figure 8. PCLK waveform in subsampled modes
Pixel n D[0:7] VGA PCLK QVGA D0 D1 D2 Pixel n+1 D3 Pixel n+2 D4 D5
It is possible to use the crop module and the sub-sampler together to achieve almost any required image size. When using the crop and subsampling functions together then the number of lines in a frame must be an integer multiple of the subsample ratio.
6.2
Frame rate control
The VL6524/VS6524 features an extremely flexible frame rate controller. Using registers uwDesiredFrame Rate_Num (MSB), uwDesiredFrame Rate_Num (LSB) and bDesiredFrameRate_ Den any desired frame rate between 1 and 30 fps can be selected (see Table 14: Frame rate control for register description). To program a required frame rate of 7.5 fps the numerator can be set to 15 and the denominator to 2. The default frame rate is 30 fps. Slower frame rates are achieved by adding interframe lines. This results in a longer frame period and therefore a longer period over which integration is possible. Due to the longer
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VL6524/VS6524
Output frame size control
integration time available slower frame rates have improved performance in low light conditions.
6.2.1
Horizontal mirror and vertical flip
The image data output from the VL6524/VS6524 can be mirrored horizontally or flipped vertically (or both). These functions are available in the Pipe setup bank0 control register bank.
6.3
ViewLive Operation
ViewLive is an option which allows different size, format and image settings to be applied to alternate frames of the output data. The controls for ViewLive function are found in the View live control register bank where the fEnable register allows the host to enable or disable the function and the InitalPipeSetupBank register selects which pipe setup bank is output first (see Table 18: View live control for register description).
Video pipe setup
The key controls for VL6524/VS6524 video pipe setup are grouped into register banks called Pipe setup bank0 control and Pipe setup bank1 control.
Pipe setup bank0 control setup is used when ViewLive is disabled.
When ViewLive is enabled the output data switches between Pipe setup bank0 control and Pipe setup bank1 control on each alternate frame. Figure 9. ViewLive frame output format
Frame output
Active video Pipe setup bank0
Interline Blanking
Interframe Blanking
Active Video Pipe setup bank1
Interline Blanking
Interframe Blanking
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Output frame size control
VL6524/VS6524
6.4
Context switching
It is possible to control which pipe setup bank is used and to switch between banks without the need to pause streaming, the change will occur at the next frame boundry after the change to the register has been made. For example this function allows the VL6524/VS6524 to stream an output targetting a display (e.g. RGB 444) and switch to capture an image (e.g. YUV 4:2:2) with no need to pause streaming or enter any other operating mode. The register bNonViewLive_ ActivePipeSetupBank allows selection of the pipe setup bank (see Table 15: Pipe setup bank selection).
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VL6524/VS6524
Output data formats
7
Output data formats
The VL6524/VS6524 supports the following data formats:

YUV4:2:2 RGB565 RGB444 (encapsulated as 565) RGB444 (zero padded) Bayer 10-bit
In all output formats there are 2 output bytes per pixel. The required data format is selected using the bdataFormat0 register described in Table 16. The various options available for each format are controlled using the bRgbSetup and bYuvSetup registers (Table 29).
7.1
YUV 4:2:2 data format
YUV 422 data format requires 4 bytes of data to represent 2 adjacent pixels. ITU601-656 defines the order of the Y, Cb and Cr components as shown in Figure 10. Figure 10. Standard Y Cb Cr data order
Cb
Y
Cr
Y
Cb
Y
Cr
Y
Cb
Y
Cr
Y
4-byte data packet
The VL6524/VS6524 bYuvSetup register can be programmed to change the order of the components as follows: Figure 11. Y Cb Cr data swapping options
Cb first Components order in 4-byte data packet 1st 2nd 3rd Y Cb Y Cr Cb Y Cr Y Y Cr Y Cb Y first
4th Cr Y Cb Y
1 DEFAULT 0 1 0
1 1 0 0
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Output data formats
VL6524/VS6524
7.2
RGB and Bayer data formats
The VL6524/VS6524 can output RGB data in the following formats:

RGB565 RGB444 (encapsulated as RGB565) RGB444 (zero padded) Bayer 10-bit
Note:
Pixels in Bayer 10-bit data output are defect corrected, correctly exposed and white balanced. Any or all of these functions can be disabled.
In each of these modes 2 bytes of data are required for each output pixel. The encapsulation of the data is shown in Figure 12.
Figure 12. RGB and Bayer data formats (1) RGB565 data packing Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 B3 2 B2 1 B1 0 B0
R4 R 3 R2 R1 R0 G 5 G 4 G 3 second byte (2) RGB 444 packed as RGB565 Bit 7 6 5 4 3 1 2 1 0 Bit
G2 G1 G0 B4
first byte
7 G0
6 1
5 0
4 B3
3 B2
2 B1
1 B0
0 1
R3 R2 R1 R0
G3 G2 G1
second byte (3) RGB 444 zero padded Bit 7 0 6 0 5 0 4 0 3 2 1 0 Bit 7 6 5
first byte
4
3
2 B2
1 B1
0 B0
R3 R 2 R1 R0
G3 G2 G1 G0 B 3 first byte
second byte (4) Bayer 10-bit Bit 7 1 6 0 5 1 4 0 3 1 2 0 1 b9 0 b8 Bit 7 b7 6 b6 5 b5
4 b4
3 b3
2 b2
1 b1
0 b0
second byte
first byte
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VL6524/VS6524
Output data formats
7.2.1
Manipulation of RGB data
It is possible to modify the encapsulation of the RGB data in a number of ways:

swap the location of the RED and BLUE data reverse the bit order of the individual color channel data reverse the order of the data bytes themselves
7.2.2
Dithering
An optional dithering function can be enabled for each RGB output mode to reduce the appearance of contours produced by RGB data truncation. This is enabled through the DitherControl register (Table 28: Dither control).
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Data synchronization methods
VL6524/VS6524
8
Data synchronization methods
External capture systems can synchronize with the data output from VL6524/VS6524 in one of two ways: 1. 2. Synchronization codes are embedded in the output data Via the use of two additional synchronization signals: VSYNC and HSYNC
Both methods of synchronization can be programmed to meet the needs of the host system.
8.1
Embedded codes
The embedded code sequence can be inserted into the output data stream to enable the external host system to synchronize with the output frames. The code consists of a 4-byte sequence starting with 0xFF, 0x00, 0x00. The final byte in the sequence depends on the mode selected. Two types of embedded codes are supported by the VL6524/VS6524: Mode 1 (ITU656) and Mode 2. The bSyncCodeSetup register is used to select whether codes are inserted or not and to select the type of code to insert (Table 29: Output formatter control). When embedded codes are selected each line of data output contains 8 additional clocks: 4 before the active video data and 4 after it.
8.1.1
Prevention of false synchronization codes
The VL6524/VS6524 is able to prevent the output of 0xFF and/or 0x00 data from being misinterpreted by a host system as the start of synchronization data. This function is controlled the bCodeCheckEnable register (Table 29: Output formatter control).
8.1.2
Mode 1(ITU656 compatible)
The structure of an image frame with ITU656 codes is shown in Figure 13.
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VL6524/VS6524 Figure 13. ITU656 frame structure with even codes
Line 1
Data synchronization methods
SAV 80
Frame of image data
EAV 9D
Line 480 SAV AB Frame blanking period EAV B6
The synchronization codes for odd and even frames are listed in Table 3 and Table 4. By default all frames output from the VL6524/VS6524 are EVEN. It is possible to set all frames to be ODD or to alternate between ODD and EVEN using the SyncCodeSetup register in the Output formatter control register bank.
Table 3.
ITU656 embedded synchronization code definition (even frames)
Name Description Line start - active Line end - active Line start - blanking Line end - blanking 4-byte sequence FF 00 00 80 FF 00 00 9D FF 00 00 AB FF 00 00 B6
SAV EAV SAV (blanking) EAV (blanking)
Line blanking period
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Data synchronization methods
VL6524/VS6524
8.1.3
Mode 2
Table 4.
ITU656 embedded synchronization code definition (odd frames)
Name Description Line start - active Line end - active Line start - blanking Line end - blanking 4-byte sequence FF 00 00 C7 FF 00 00 DA FF 00 00 EC FF 00 00 F1
SAV EAV SAV (blanking) EAV (blanking)
The structure of a mode 2 image frame is shown Figure 14. Figure 14. Mode 2 frame structure (VGA example)
FS Line 1
LS
Frame of image data
LE
Line 480 Frame blanking period
FE
For mode 2, the synchronization codes are as listed in Table 5. Table 5. Mode 2 - embedded synchronization code definition
Name LS LE Line start Line end Description 4-byte sequence FF 00 00 00 FF 00 00 01
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Line blanking period
VL6524/VS6524 Table 5.
Data synchronization methods Mode 2 - embedded synchronization code definition
Name Description Frame Start Frame End 4-byte sequence FF 00 00 02 FF 00 00 03
FS FE
8.2
VSYNC and HSYNC
The VL6524/VS6524 can provide two programmable hardware synchronization signals: VSYNC and HSYNC. The position of these signals within the output frame can be programmed by the user or an automatic setting can be used where the signals track the active video portion of the output frame regardless of its size.
8.2.1
Horizontal synchronization signal (HSYNC)
The HSYNC signal is controlled by the bHSyncSetup register (Table 29). The following options are available:

enable/disable select polarity all lines or active lines only manual or automatic
In automatic mode the HSYNC signal envelops all the active video data on every line in the output frame regardless of the programmed image size. Line codes (if selected) fall outside the HSYNC envelope as shown in Figure 15. Figure 15. HSYNC timing example
hsync=0 hsync=1
BLANKING DATA EAV Code
FF 00 00 XY 80 10 80 10 80 10
ACTIVE VIDEO DATA SAV Code
80 10 FF 00 00 XY D0 D1 D2 D3 D0 D1 D2 D3
EAV Code
D2 D3 FF 00 00 XY
If manual mode is selected then the pixel positions for HSYNC rising edge and falling edge are programmable. The pixel position for the rising edge of HSYNC is programmed in the bHsyncRisingH, bHsyncRisingL registers. The pixel position for the falling edge of HSYNC is programmed in the bHsyncFallingH and bHsyncFallingL registers (Table 29).
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Data synchronization methods
VL6524/VS6524
8.2.2
Vertical synchronization (VSYNC)
The VSYNC signal is controlled by the bVSyncSetup register. The following options are available:

enable/disable select polarity manual or automatic
In automatic mode the VSYNC signal envelops all the active video lines in the output frame regardless of the programmed image size as shown in Figure 16. Figure 16. VSYNC timing example
BLANKING V=0 V=1 ACTIVE VIDEO
vsync
BLANKING
V=0 V=1
ACTIVE VIDEO
If manual mode is selected then the line number for VSYNC rising edge and falling edge is programmable. The rising edge of VSYNC is programmed in the bVsyncRisingLineH, bVsyncRisingLineL registers, the pixel position for VSYNC rising edge is programmed in the bVsyncRisingPixelH and bVsyncRisingPixelL registers. Similarly the line count for the falling edge position is specified in the bVsyncFallingLineH and bVsyncFallingLineL registers, and the pixel count is specified in the bVsyncFallingPixelH and bVsyncFallingPixelL registers described in Table 29: Output formatter control.
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VL6524/VS6524
Getting started
9
9.1
Getting started
Initial power up
Before any communication is possible with the VL6524/VS6524 the following steps must take place: 1. 2. 3. 4. Apply VDD (1.8V or 2.8V) Apply AVDD (2.8V) Apply an external CLOCK (6.5 MHz to 26 MHz) Assert CE line HIGH
These steps can all take place simultaneously. After these steps are complete a delay of 200 s is required before any IC communication can take place, see Figure 3: Power up sequence.
9.2
Minimum startup command sequence
1. Enable the microprocessor - before any commands can be sent to the VL6524/VS6524, the internal microprocessor must be enabled by writing the value 0x06 to the MicroEnable register 0xC003 (Table 7: Low-level control registers). Enable the digital I/O - after power up the digital I/O of the VL6524/VS6524 is in a highimpedance state (`tri-state'). The I/O are enabled by writing the value 0x01 to the Enable I/O register 0xC034 (Table 7: Low-level control registers). The user can then program the system clock frequency and setup the required output format before placing the VL6524/VS6524 in RUN mode by writing 0x02 to the bUserCommand register 0x0180 (Table 9: Mode control).
2.
3.
The above three commands represent the absolute minimum required to get video data output. The default configuration results in an output of VGA, 30 fps, YUV data format with ITU embedded codes requiring a external clock frequency of 12MHz. In practice the user is likely to require to write some additional setup information prior to receive the required data output.
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Host communication - IC control interface
VL6524/VS6524
10
Host communication - IC control interface
The interface used on the VL6524/VS6524 is a subset of the IC standard. Higher level protocol adaptations have been made to allow for greater addressing flexibility. This extended interface is known as the V2W interface.
V2W protocol layer
Protocol
A message contains two or more bytes of data preceded by a START (S) condition and followed by either a STOP (P) or a repeated START (Sr) condition followed by another message. STOP and START conditions can only be generated by a V2W master. After every byte transferred the receiving device must output an acknowledge bit which tells the transmitter if the data byte has been successfully received or not. The first byte of the message is called the device address byte and contains the 7-bit address of the V2W slave to be addressed plus a read/write bit which defines the direction of the data flow between the master and the slave. The meaning of the data bytes that follow device address changes depending whether the master is writing to or reading from the slave. Figure 17. Write message
S DEV ADDR R/W A DATA A 2 Index Bytes DATA A DATA N Data Byte A/A P
`0' (Write)
From Master to Slave
From Slave to Master
For the master writing to the slave the device address byte is followed by 2 bytes which specify the 16-bit internal location (index) for the data write. The next byte of data contains the value to be written to that register index. If multiple data bytes are written then the internal register index is automatically incremented after each byte of data transferred. The master can send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a STOP condition or sends a repeated START (Sr). Figure 18. Read message
S DEV ADDR R/W A DATA A DATA A P
`1' (Read)
1 or more Data Byte
From Master to Slave
From Slave to Master
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VL6524/VS6524
Host communication - IC control interface
For the master reading from the slave the device address is followed by the contents of last register index that the previous read or write message accessed. If multiple data bytes are read then the internal register index is automatically incremented after each byte of data read. A read message is terminated by the bus master generating a negative acknowledge after reading a final byte of data. A message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation.
Detailed overview of the message format
Figure 19. Detailed overview of message format
1 2 3 4 5 6
S (Sr)
7-bit Device Address
R/W
A
8-bit Data
A (A)
P (Sr)
P SDA MSB SCL S or Sr LSB MSB LSB Sr Sr or P
1
2
7
8
9
1
2
7
8
9
START or repeated START condition
Device Address
R/W Bit 0 - Write 1 - Read
ACK signal from slave
Data byte from transmitter R/W=0 - Master R/W=1 - Slave
ACK signal from receiver
STOP or repeated Start condition
The V2W generic message format consists of the following sequence 1. 2. Master generates a START condition to signal the start of new message. Master outputs, MS bit first, a 7-bit device address of the slave the master is trying to communicate with followed by a R/W bit.
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Host communication - IC control interface Figure 20. Device addresses
Sensor Address 0 0 1 0 0 0
VL6524/VS6524
0
R/W
Sensor write Address 20H
0
0
1
0
0
0
0
0
Sensor read Address 21H
0
0
1
0
0
0
0
1
a) b) 3. 4.
R/W = 0 then the master (transmitter) is writing to the slave (receiver). R/W = 1 the master (receiver) is reading from the slave (transmitter).
The addressed slave acknowledges the device address. Data transmitted on the bus a) b) When a write is performed then master outputs 8-bits of data on SDA (MS Bit first). When a read is performed then slave outputs 8-bits of data on SDA (MS Bit First). When a write is performed slave acknowledges data. When a read is performed master acknowledges data.
5.
Data receive acknowledge a) b)

Repeat 4 and 5 until all the required data has been written or read. Minimum number of data bytes for a read =1 (Shortest Message length is 2-bytes). The master outputs a negative acknowledge for the data when reading the last byte of data. This causes the slave to stop the output of data and allows the master to generate a STOP condition. Master generates a STOP condition or a repeated START.
6.
Data valid
The data on SDA is stable during the high period of SCL. The state of SDA is changed during the low phase of SCL. The only exceptions to this are the start (S) and stop (P) conditions as defined below. (See Figure 33: Timing specification and Table 38: Timing specification). Figure 21. SDA data valid
SDA
SCL Data line stable Data valid Data change Data line stable Data valid
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VL6524/VS6524
Host communication - IC control interface
Start (S) and Stop (P) conditions
A START (S) condition defines the start of a V2W message. It consists of a high to low transition on SDA while SCL is high. A STOP (P) condition defines the end of a V2W message. It consists of a low to high transition on SDA while SCL is high. After STOP condition the bus is considered free for use by other devices. If a repeated START (Sr) is used instead of a stop then the bus stays busy. A START (S) and a repeated START (Sr) are considered to be functionally equivalent. Figure 22. START and STOP conditions
SDA
SCL
S START condition
P STOP condition
Acknowledge
After every byte transferred the receiver must output an acknowledge bit. To acknowledge the data byte receiver pulls SDA during the 9th SCL clock cycle generated by the master. If SDA is not pulled low then the transmitter stops the output of data and releases control of the bus back to the master so that it can either generate a STOP or a repeated START condition. Figure 23. Data acknowledge
SDA data output by transmitter Negative acknowledge (A) SDA data output by receiver
Acknowledge (A) SCL clock from master S START condition 1 2 8 9
Clock pulse for acknowledge
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Host communication - IC control interface
VL6524/VS6524
Index space
Communication using the serial bus centres around a number of registers internal to the either the sensor or the co-processor. These registers store sensor status, set-up, exposure and system information. Most of the registers are read/write allowing the receiving equipment to change their contents. Others (such as the chip id) are read only. The internal register locations are organized in a 64k by 8-bit wide space. This space includes "real" registers, SRAM, ROM and/or micro controller values. Figure 24. Internal register index space
8 bits
65535 65534 65533 65532
130
16-bit Index / 8-bit Data Format 64k by 8-bit wide index space (Valid Addresses 0-65535)
129 128 127 126 125
4 3 2 1 0
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VL6524/VS6524
Host communication - IC control interface
Types of messages
This section gives guidelines on the basic operations to read data from and write data to VL6524/VS6524. The serial interface supports variable length messages. A message contains no data bytes or one data byte or many data bytes. This data can be written to or read from common or different locations within the sensor. The range of instructions available are detailed below. Single location, single byte data read or write. Write no data byte. Only sets the index for a subsequent read message. Multiple location, multiple data read or write for fast information transfers. Any messages formats other than those specified in the following section should be considered illegal.
Random location, single data write
For the master writing to the slave the R/W bit is set to zero. The register index value written is preserved and is used by a subsequent read. The write message is terminated with a stop condition from the master. Figure 25. Random location, single write
16-bit Index, 8-bit Data, Random Location, Single Data Write
Previous Index Value, K S DEV ADDR R/W A DATA A DATA A DATA Index M A/A P
`0' (Write)
INDEX[15:8]
INDEX[7:0]
DATA[7:0]
Index[15:0] value, M From Master to Slave From Slave to Master
DATA[7:0]
S = START Condition Sr = repeated START P = STOP Condition
A = Acknowledge A = Negative Acknowledge
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Host communication - IC control interface
VL6524/VS6524
Current location, single data read
For the master reading from the slave the R/W bit is set to one. The register index of the data returned is that accessed by the previous read or write message. The first data byte returned by a read message is the contents of the internal index value and NOT the index value. This was the case in older V2W implementations. Note that the read message is terminated with a negative acknowledge (A) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. This is because if the data sent by the slave is all zeros, the SDA line cannot rise, which is part of the stop condition. Figure 26. Current location, single read
16-bit index, 8-bit data current location, single data read
Previous Index Value, K
S
DEV ADDR R/W A
DATA
A
P
`1' (Read)
DATA[7:0]
DATA[7:0]
From Master to Slave From Slave to Master
S = START Condition Sr = repeated START P = STOP Condition
A = Acknowledge A = Negative Acknowledge
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VL6524/VS6524
Host communication - IC control interface
Random location, single data read
When a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written first, specifying the index. The read message then completes the message sequence. To avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the write and read messages. As mentioned in the previous example, the read message is terminated with a negative acknowledge (A) from the master. Figure 27. Random location, single data read
16-bit Index, 8-bit data random index, single data read
Previous Index Value, K No Data Write Index M Data Read
S
DEV ADDR R/W A
DATA
A
DATA
A
Sr
DEV ADDR R/W A
DATA
A
P
`0' (Write) INDEX[15:8] INDEX[7:0]
`1' (Read)
DATA[7:0] DATA[7:0]
INDEX[15:0] value, M
From Master to Slave From Slave to Master
S = START Condition Sr = repeated START P = STOP Condition
A = Acknowledge A = Negative Acknowledge
Multiple location write
For messages with more than 1 data byte the internal register index is automatically incremented for each byte of data output, making it possible to write data bytes to consecutive adjacent internal registers without having to send explicit indexes prior to sending each data byte. Figure 28. Multiple location write
16-bit index, 8-bit data multiple location write
Previous Index Value, K S DEV ADDR R/W A DATA A DATA A Index M DATA A Index (M + N - 1) DATA A/A P
`0' (Write) INDEX[15:8] INDEX[7:0] DATA[7:0] DATA[7:0] DATA[7:0] DATA[7:0] N Bytes of Data
INDEX[15:0] value, M
From Master to Slave From Slave to Master
S = START Condition Sr = repeated START P = STOP Condition
A = Acknowledge A = Negative Acknowledge
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Host communication - IC control interface
VL6524/VS6524
Multiple location read stating from the current location
In the same manner to multiple location writes, multiple locations can be read with a single read message. Figure 29. Multiple location read
16-bit Index, 8-bit data multiple location read
Previous Index Value, K S DEV ADDR R/W A DATA A Index K+1 DATA A DATA Index (K + N - 1) A P
`1' (Read)
DATA[7:0] DATA[7:0] DATA[7:0] DATA[7:0] N Bytes of Data DATA[7:0] DATA[7:0]
From Master to Slave From Slave to Master
S = START Condition Sr = repeated START P = STOP Condition
A = Acknowledge A = Negative Acknowledge
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VL6524/VS6524
I2C Combined Format Specification
DATA Write Data (N bytes + acknowledge) A DATA A/A Sr DEV ADDR R/W A DATA A DATA A P
S
DEV ADDR R/W A
`0' (Write)
`1' (Read)
Read Data (R bytes + acknowledge
16-bit Index, 8-bit Data Random Index, Multiple Data Read
Previous Index Value, K No Data Write Index M Data Read Index (M + N - 1)
S
DEV ADDR R/W A
DATA
A
DATA
A
Sr
DEV ADDR R/W A
DATA
A
DATA
A
P
`0' (Write) INDEX[15:8] INDEX[15:0] value, M INDEX[7:0]
`1' (Read)
DATA[7:0] DATA[7:0] DATA[7:0] DATA[7:0] N Bytes of Data A = Acknowledge A = Negative Acknowledge
Figure 30. Multiple location read starting from a random location
From Master to Slave
S = START Condition Sr = repeated START P = STOP Condition
Host communication - IC control interface
From Slave to Master
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Register map
VL6524/VS6524
11
Register map
The VL6524/VS6524 IC write address is 0x20. All IC locations contain an 8-bit byte. However, certain parameters require 16 bits to represent them and are therefore stored in more than 1 location.
Note:
For all 16 bit parameters the MSB register must be written before the LSB register.
The data stored in each location can be interpreted in different ways as shown below. Register contents represent different data types as described in Table 6. Table 6. Data type
Description Integer parameter. Multiple field registers - 16 bit parameter Bit field register - individual bits must be set/cleared Coded register - function depends on value written Float Value
Data Type I M B C F
Float number format
Float 900 is used in ST co-processors to represent floating point numbers in 2 bytes of data. It conforms to the following structure: Bit[15] = Sign bit (1 represents negative) Bit[14:9] = 6 bits of exponent, biased at decimal 31 Bit[8:0] = 9 bits of mantissa To convert a floating point number to Float 900, use the following procedure:

represent the number as a binary floating point number. Normalize the mantissa and calculate the exponent to give a binary scientific representation of 1.xxxxxxxxx * 2^y. The x symbols should represent 9 binary digits of the mantissa, round or pad with zeros to achieve 9 digits in total. Remove the leading 1 from the mantissa as it is redundant. To calculate the y value Bias the exponent by adding to 31 decimal then converting to binary. The data can then be placed in the structure above.
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VL6524/VS6524
Register map
Example
Convert -0.41 to Float 900 Convert the fraction into binary by successive multiplication by 2 and removal of integer component
0.41 * 2 = 0.82 0.82 * 2 = 1.64 0.64 * 2 = 1.28 0.28 * 2 = 0.56 0.56 * 2 = 1.12 0.12 * 2 = 0.24 0.24 * 2 = 0.48 0.48 * 2 = 0.96 0.96 * 2 = 1.92 0.92 * 2 = 1.84 0.84 * 2 = 1.68 0.68 * 2 = 1.36 0.36 * 2 = 0.72 0 1 1 0 1 0 0 0 1 1 1 1 0
This gives us -0.0110100011110. We then normalize by moving the decimal point to give - 1.10100011110 * 2^-2. The mantissa is rounded and the leading zero removed to give 101001000. We add the exponent to the bias of 31 that gives us 29 or 11101. A leading zero is added to give 6 bits 011101. The sign bit is set at 1 as the number is negative. This gives us 1011 1011 0100 1000 as our Float 900 representation or BB48 in hex. To convert the encoded representation back to a decimal floating point, we can use the following formula. Real is = (-1)^sign * ((512+mantissae)>> 9) * 2^(exp-31) Thus to convert BB48 back to decimal, the following procedure is followed: Note that >>9 right shift is equal to division by 2^9. Sign = 1 Exponent = 11101 (29 decimal) Mantissa = 101001000 (328 decimal) This gives us: real = (-1)^1 * ((512+328)/2^9) * 2^(29-31) real = -1 * (840/512) * 2^(-2) real = -1 * 1.640625 * 0.25 real = -0.41015625 When compared to the original -0.41, we see that some rounding errors have been introduced.
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Register map
VL6524/VS6524
Low level control registers
Table 7. Low-level control registers
Name MicroEnable Enable I/O Index 0xC003 0xC034 R/W R/W R/W Data Type C B Format default 0x38 0x00 Description 0x06 - clocks enabled set bit[0] to enable IO
Note:
The default values for the above registers are true when the device is powered on, Ext. Clk input is present and the CE pin is high. All other registers can be read when the Clock enable register is set to 0x06.
Device parameters [read only]
Table 8. Device parameters
Name uwDeviceId (MSB) uwDeviceId (LSB) bFirmwareVsnMajor bFirmwareVsnMinor bPatchVsnMajor bPatchVsnMinor Index 0x0001 0x0002 0x0004 0x0006 0x0008 0x000a R/W R R R R R R Data Type I I I I I I Format default 0x02 0x020c = 524 0x0c 0x01 0x01 0x00 0x00 Firmware version 0x0101 = 1.1 Patch version 0x0000 Description
Mode control
Table 9. Mode control
Name Index R/W Data Type Format default Description 0x00 - UNINITIALISED 0x01 - BOOT 0x02 - RUN 0x03 - PAUSE 0x04 - STOP 0x05 - FLASHGUN
bUserCommand
0x0180
RW
C
0
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VL6524/VS6524
Register map
Mode Status [read only]
Table 10. Mode status
Index R/W Data Type Format default Description 0x10 - RAW 0x21 - Waiting for BOOT 0x22 - PAUSED 0x26 - Waiting for RUN 0x31 - RUNNING 0x32 - Waiting for PAUSE 0x40 - FLASHGUN 0x50 - STOPPED
Name
bState
0x0202
R
C
0x10
RunModeControl
Table 11. RunModeControl
Index R/W Data Type B Format default 0x01 0x00 = False 0x01 = True Description
Name
fMeteringOn
0x0280
R/W
Clock manager input control
Table 12. Clock manager input control
Index 0x060b 0x060c 0x060e 0x0610 R/W R/W R/W R/W R/W Data Type I I I B Format default 0x00 0x0c 0x01 0x00 Description
Name uwExtClockFreqNum (MSB) uwExtClockFreqNum (LSB) bExtClockFreqDen bEnableGlobalSystem ClockDivision
Specifies the external clock frequency numerator Default = 12 MHz Specifies the external clock frequency denominator 0x00 = False 0x01 = True -system clock division by 2
Power management control
Table 13. Power management control
Index R/W Data Type Format default Description Time (ms) from pausing streaming to entering stop. In the range 5 to 154 ms 0xff - disable
Name
bTimeToPowerdown
0x0580
R/W
I
0x0f
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Register map
VL6524/VS6524
Frame rate control
Table 14. Frame rate control
Index 0x0d81 0x0d82 0x0d84 R/W R/W R/W R/W Data Type I I I Format default 0x00 0x1e 0x01 Description
Name uwDesiredFrame Rate_Num (MSB) uwDesiredFrame Rate_Num (LSB) bDesiredFrameRate_ Den
Numerator for the Frame Rate Default = 30 fps
Denominator for the Frame Rate
Pipe setup bank selection
Table 15. Pipe setup bank selection
Index R/W Data Type I Format default 0x00 Description 0x00 -Pipe setup bank0 used 0x01 -Pipe setup bank1 used
Name bNonViewLive_ ActivePipeSetupBank
0x0302
R/W
Pipe setup bank0 control
Table 16. Pipe setup bank0 control
Index R/W Data Type Format default Description Required output dimension 0x01 - ImageSize_VGA 0x02 - ImageSize_QVGA 0x03 - ImageSize_QQVGA 0x04 - ImageSize_Manual 0x01 = Minimum sub-sample corresponding to no sub-sampling. MAX = 0x06 0x00 = False - 0x01 = True Horizontal start point for manual crop uwCropHStartLSB0 uwCropHSizeMSB0 uwCropHSizeLSB0 uwCropVStartMSB0 uwCropVStartLSB0 uwCropVSizeMSB0 uwCropVSizeLSB0 0x0388 0x038b 0x038c 0x038f 0x0390 0x0393 0x0394 R/W R/W R/W R/W R/W R/W R/W MI MI MI MI MI MI MI 0x00 0x00 Horizontal size for manual crop 0x00 0x00 Vertical start point for manual crop 0x00 0x00 Vertical size for manual crop 0x00
Name
bImageSize0
0x0380
R/W
C
0x01
bSubSample0 fEnableCrop0 uwCropHStartMSB0
0x0382 0x0384 0x0387
R/W R/W R/W
I B MI
0x01 0x00 0x00
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VL6524/VS6524 Table 16. Pipe setup bank0 control
Index R/W Data Type Format default
Register map
Name
Description 0x00 = YCbCr_JFIF 0x01 = YCbCr_Rec601 0x02 = YCbCr_Custom 0x03 = RGB_565 0x04 = RGB_565_Custom 0x05 = RGB_444 0x06 = RGB_444_Custom 0x07 = reserved 0x08 = Bayer output VP 0x04 = Bayer output right shifted 0x05 = Bayer output left shifted Contrast control (%) Color saturation control (%) Gamma settings 0x00 = Gamma_Linear 0x10 = Gamma SMPTE 240M 0x1F = Gamma_Max Horizontal mirror control, 0x00 = False - 0x01 = True Vertical mirror control, 0x00 = False - 0x01= True
bdataFormat0
0x0396
R/W
C
0x01
bBayerOutput Alignment0 bContrast0 bColorSaturation0
0x398 0x039a 0x039c
R/W
C I I
0x04 0x79 0x7d
bGamma0
0x039e
I
0x0f
fHorizontaiMirror0 fVerticalFlip0
0x03a0 0x03a2
B B
0x00 0x00
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Register map
VL6524/VS6524
Pipe Setup Bank1 Control
Table 17. Pipe setup bank1 control
Index R/W Data Type Format default Description Required output dimension 0x01 = ImageSize_VGA 0x02 = ImageSize_QVGA 0x03 = ImageSize_QQVGA 0x04 = ImageSize_Manual 0x01 = Minimum sub-sample corresponding to no sub-sampling. MAX = 0x06 0x00 = False - 0x01 = True Horizontal start point for manual crop uwCropHStartLSB1 uwCropHSizeMSB1 uwCropHSizeLSB1 uwCropVStartMSB1 uwCropVStartLSB1 uwCropVSizeMSB1 uwCropVSizeLSB1 0x0408 0x040b 0x040c 0x040f 0x0410 0x0413 0x0414 R/W R/W R/W R/W R/W R/W R/W MI MI MI MI MI MI MI 0x00 0x00 Horizontal size for manual crop 0x00 0x00 Vertical start point for manual crop 0x00 0x00 Vertical size for manual crop 0x00 0x00 = YCbCr_JFIF 0x01 = YCbCr_Rec601 0x02 = YCbCr_Custom 0x03 = RGB_565 0x04 = RGB_565_Custom 0x05 = RGB_444 0x06 = RGB_444_Custom 0x07 = BayerVPBypass 0x08 = BayerThroughVP 0x04 = Bayer output right shifted 0x05 = Bayer output left shifted Contrast control (%) Color saturation control (%) Gamma settings 0x00 = Gamma_Linear 0x10 = Gamma SMPTE 240M 0x1F = Gamma_Max Horizontal mirror control 0x00 = False, 0x01 = True Vertical mirror control 0x00 = False , 0x01 = True
Name
bImageSize1
0x0400
R/W
C
0x01
bSubSample1 fEnableCrop1 uwCropHStartMSB1
0x0402 0x0404 0x0407
R/W R/W R/W
C B MI
0x01 0x00 0x00
bdataFormat1
0x0416
R/W
C
0x01
bBayerOutput Alignment1 bContrast1 bColorSaturation1
0x0418 0x041a 0x041c
R/W R/W R/W
C I I
0x04 0x79 0x7d
bGamma1
0x041e
R/W
I
0x0f
fHorizontalMirror1 fVerticalFlip1
0x0420 0x0422
R/W R/W
B B
0x00 0x00
48/70
VL6524/VS6524
Register map
View live control
Table 18. View live control
Index R/W Data Type B Format default 0x00 Description Enable ViewLive mode 0x00 = False - 0x01 = True When ViewLive mode is enabled, this register selects which PipeSetupBank the first frame output uses, 0x00 = PipeSetupBank0 0x01 = PipeSetupBank1
Name
fEnable
0x0480
R/W
InitalPipeSetupBank
0x0482
R/W
C
0x00
White balance control
Table 19. White balance control
Index R/W Data Type Format default Description White balance mode selection: 0x00 = OFF - No White balance, all gains are unity in this mode 0x01 = AUTOMATIC 0x03 = MANUAL_RGB - gains are applied manually using registers below 0x04 = DAYLIGHT_PRESET 0x05 = TUNGSTEN_PRESET 0x06 = FLUORESCENT_PRESET 0x07 = HORIZON_PRESET 0x08 = MANUAL_COLOUR_TEMP 0x09 = FLASHGUN_PRESET User setting for Red Channel gain User setting for Green Channel gain User setting for Blue Channel gain
Name
WhiteBalanceMode
0x1380
R/W
C
0x01
bManualRedGain bManualGreenGain bManualBlueGain fpRedGainforFlashgun MSB fpRedGainforFlashgun LSB fpGreenGainfor Flashgun MSB fpGreenGainfor Flashgun LSB fpBlueGainfor Flashgun MSB fpBlueGainfor Flashgun LSB
0x1382 0x1384 0x1386 0x138b 0x138c 0x138f 0x1390 0x1393 0x1394
R/W R/W R/W R/W R/W R/W R/W R/W R/W
I I I MF MF MF MF MF MF
0x00 0x00 0x00 0x3e
Red Channel gain for Flashgun Code float - Default 0x3e66 = 1.199219 0x66 0x3e Green Channel gain for Flashgun Code float - Default 0x3e00 = 1.000000 0x00 0x3e Blue Channel gain for Flashgun Code float . Default 0x3e33 = 1.099609 0x33
49/70
Register map
VL6524/VS6524
Exposure control
Table 20. Exposure control
Index R/W Data Type Format default Description 0x00 = AUTOMATIC_MODE 0x01 = COMPILED_MANUAL_ MODE - The desired exposure time is set manually in the Manual Exposure registers and the exposure parameters are calculated by the algorithm. 0x02 = DIRECT_MANUAL_ MODE - The exposure parameters are input directly. 0x03 = FLASHGUN_MODE The exposure parameters are set manually. Weights associated with the zones to calculate the mean statistics. Exposure Weight is Centered or Backlit or Flat. 0x00 = ExposureMetering_flat - Uniform gain associated with all pixels 0x01 = ExposureMetering_backlit: more gain associated with centre and bottom pixels 0x02 = ExposureMetering_centred - more gain associated with centre pixels Exposure Time for Compiled Manual Mode in seconds. Numerator / Denominator gives required exposure time Exposure Compensation - a user choice for setting the runtime target. A unit of exposure compensation corresponds to 1/6 EV. This is a signed register. Freeze auto exposure 0x00 = False 0x01 = True User Maximum Integration Time in microseconds. This control takes in the maximum integration time that host would like to support. This in turn gives an idea of the degree of "wobbly pencil effect" acceptable by Host. Default 0x647f = 654336
Name
bExposureMode
0x1080
R/W
C
0x00
bExposureMetering
0x1082
R/W
C
0x00
bManualExposure Time_Num bManualExposure Time_Den iExposure Compensation
0x1084 0x1086
R/W R/W
I I
0x01 0x1e
0x1090
R/W
I
0x00
fFreezeAuto Exposure fpUserMaximum IntegrationTime (MSB)
0x10b4
R/W
B
0x00
0x10b7
R/W
MF
0x64
fpUserMaximum IntegrationTime (LSB)
0x10b8
R/W
MF
0x7f
50/70
VL6524/VS6524
Register map
Exposure status (Read only)
Table 21. Exposure status
Index 0x121d 0x121e R/W R R Data Type MF MF Format default Description Present exposure time as calculated by the compiler taking into account the framerate used.
Name fpCompiledTime (MSB) fpCompiledTime (LSB)
Exposure algorithm control
Table 22. Exposure algorithm control
Index R/W Data Type Format default Description Control exposure leaky integrator. Set to 0 for reactive systems. Set to 4 for more stable systems.
Name
bLeakShift
0x113c
R/W
I
0x02
Flashgun control
Table 23. Flashgun control
Index R/W Data Type Format default Description Manual flashgun control(1) 0x00 = Flash off 0x01 = Torch (FSO pin high) 0x02 = Flash pulse This is used to set the duration of the flash. The value equals the line in the frame during which the flashgun pulse is switched off.
Name
bFlashgunMode
0x1780
R/W
C
0x00
uwFlashgunOffLine MSB uwFlashgunOffLine LSB
0x1783 0x1784
R/W R/W
MI MI
0x02 0x1c
1. The mode control register has priority over this function
51/70
Register map
VL6524/VS6524
Flicker frequency control
Table 24. Flicker frequency control
Index R/W Data Type Format default Description Modes for anti-flicker compilation. 0x00 = Inhibit 0x01 = Manual Enable Flicker free time period calculations this should be 2* AC mains frequency 0x64 = 100 = 50Hz AC freq 0x78 =120 = 60Hz AC freq Set to make the frame length compatible with the flicker free time period, 0x00 = FALSE 0x01 = TRUE
Name
bAntiFlickerMode
0x10c0
R/W
C
0x01
bLightingFreqHz
0x0c80
R/W
I
0x64
fFlickerComplatible FrameLength
0x0c82
R/W
B
0x00
Defect correction control
Table 25. Defect correction control
Index R/W Data Type B B Format default 0x00 0x00 0x00 = False 0x01 = True 0x00 = False 0x01 = True Description
Name
fDisableScytheFilter fDisableJackFilter
0x1a80 0x1b00
R/W R/W
Sharpening control
Table 26. Sharpening control
Index 0x1d80 0x1d90 R/W R/W R/W Data Type I I Format default 0x0f 0x1e Description Adjust gradient of sharpening system The coring threshold is used to stop the sharpening gain being applied to very small changes in the image (i.e. Noise).
Name bUserPeakGain bUserPeakLo Threshold
Fade to black damper control
Table 27. Fade to black damper control
Index R/W Data Type Format default Description Set to disable fade to black operation. 0x00 = False 0x01 = True
Name
fDisable
0x2000
R/W
B
0x00
52/70
VL6524/VS6524 Table 27. Fade to black damper control
Index 0x2003 0x2004 R/W R/W R/W Data Type MF MF Format default 0x00 0x00
Register map
Name fpBlackValue (MSB) fpBlackValue (LSB) fpDamperLow Threshold (MSB) fpDamperLow Threshold (LSB) fpDamperHigh Threshold (MSB) fpDamperHigh Threshold (LSB) fpMinimumOutput (MSB) fpMinimumOutput (LSB)
Description Minimum possible damper output for the colour matrix 0.0 fades to absolute black, 1.0 effectively disables fade to black. Default 0x0000 = 0 Low threshold to calculate the damper slope Default 0x67d1 =500224
0x2007 0x2008 0x200b 0x200c 0x200f 0x2010
R/W R/W R/W R/W R R
MF MF MF MF F
0x63 0xd1 0x65 0x6f
High threshold to calculate the damper slope Default 0x656f = 900096
Status value showing damper strength used F
53/70
Register map
VL6524/VS6524
Dither control
Table 28. Dither control
Index R/W Data Type Format default Description 0x00 = Dither RGB modes only 0x01 = Dither function OFF 0x02 = Dither function ON
Name
DitherControl
0x2080
R/W
C
0x00
Output formatter control
Table 29. Output formatter control
Index R/W Data Type Format default Description 0x00 - allow all output values 1 = suppress 0xFF 2 = suppress 0x00 3 = suppress 0x00 and 0xFF from output [0] Enable Sync Codes [1] Sync Code Type (0 = ITU, 1 = mode2) [2] Odd/Even field (0 =even, 1 =odd) [3] Toggle (1 = Toggle) [4] Load (set high then low over a frame boundary to consume a change applied in [2] or [3]) [0] Enable [1] Polarity [2] Active lines only [3] Automatic/manual [0] Enable [1] Polarity [2] Automatic/Manual [0] Edge (1=positive, 0 =negative) [1] Non-active level (1=high. 0 = low) [2] Enable [7] Free-running 0 = False - 1 = True Blanking MSB Blanking LSB [0] RGB 444 - zero packing [1] Swap R and B components [2] Reverse Bits [0] Cb_first [1] Y first
Name
bCodeCheckEnable
0x2100
R/W
C
0x07
bSyncCodeSetup
0x2104
R/W
B
0x01
bHSyncSetup
0x2106
R/W
B
0x0b
bVSyncSetup
0x2108
R/W
B
0x07
bPClkSetup
0x210a
R/W
B
0x05
fpPclkEn bBlankData_MSB bBlankData_LSB bRgbSetup
0x210c 0x2110 0x2112 0x2114
R/W R/W R/W R/W
B I I B
0x01 0x10 0x80 0x00
bYuvSetup
0x2116
R/W
B
0x00
54/70
VL6524/VS6524 Table 29. Output formatter control
Index 0x2118 0x211a 0x211c 0x211e 0x2120 0x2122 0x2124 0x2126 0x2128 0x212a 0x212c 0x212e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Data Type MI MI MI MI MI MI MI MI MI MI MI MI Format default 0x00 0x00 0x01 0x01 0x01 0xf2 0x00 0x01 0x00 0x03 0x00 0x07
Register map
Name bVsyncRisingLineH bVsyncRisingLineL bVsyncRisingPixelH bVsyncRisingPixelL bVsyncFallingLineH bVsyncFallingLineL bVsyncFallingPixelH bVsyncFallingPixelL bHsyncRisingH bHsyncRisingL bHsyncFallingH bHsyncFallingL
Description Line on which Vsync should rise (manual vsync must be selected) Pixel on which Vsync should rise (manual vsync must be selected) Line on which Vsync should fall (manual vsync must be selected) Pixel on which Vsync should fall (manual vsync must be selected) Pixel on which Hsync should rise (manual Hsync must be selected) Pixel on which Hsync should fall (manual Hsync must be selected)
55/70
Optical specifications
VL6524/VS6524
12
Optical specifications
Table 30. Optical specifications(1)
Parameter Optical format Effective focal length Aperture (F number) Horizontal field of view Vertical field of view Diagonal field of Depth of field(3) view(2) 46 35 57 20 -1.5 Min. Typ. 1/6 2.5 2.8 49 37 59 51 39 61 infinity 1.5 deg. deg. deg. cm % Max. Unit inch mm
TV distortion
1. All measurements made at 23C 2C 2. Value determined through calculation
3. By design the device has an acceptable quality between hyperfocal distance /2 and infinity.
12.1
Average sensitivity
The average sensitivity is a measure of the image sensor response to a given light stimulus. The optical stimulus is a white light source with a color temperature of 3200K, producing uniform illumination at the surface of the sensor package. An IR blocking filter is added to the light source. The analog gain of the sensor is set to x1. The exposure time, t, is set as 50% of maximum. The illuminance, I, is adjusted so the average sensor output code, Xlight, is roughly mid-range equivalent to a saturation level of 50%. Once Xlight has been recorded the experiment is repeated with no illumination to give a value Xdark.
Xlight - Xdark The sensitivity is then calculated as --------------------------------------- .The result is expressed in volts per luxt l second.
The sensitivity of the VS6524 is given in Table 31. Table 31. VS6524 average sensitivity
Value 0.71 Unit V/lux.s
Optical parameter Average sensitivity
56/70
VL6524/VS6524
Optical specifications
12.2
Spectral response
The spectral response for the VS6524 sensor is shown in Figure 31. Figure 31. VS6524 spectral response Quantum efficiency - Sensitivity = 0.71V/lux.sec.
Blue
35 30 25
Green
Red
QE /%
20 15 10 5 0
400
450
500
550 Wavelength /nm
600
650
700
57/70
Electrical characteristics
VL6524/VS6524
13
13.1
Electrical characteristics
Absolute maximum ratings
Table 32.
Symbol TSTO VDD AVDD Storage temperature Digital power supplies Analog power supplies
Absolute maximum ratings
Parameter Min. -40 -0.5 -0.5 Max. 85 3.3 3.3 Unit C V V
Caution:
Stress above those listed under "Absolute Maximum Ratings" can cause permanent damage to the device. This is a stress rating only and functional operations of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
13.2
Operating conditions
Table 33.
Symbol TAF TAN TAO VDD AVDD
Supply specifications
Parameter Operating temperature, functional (Camera is electrically functional) Operating temperature, nominal (Camera produces acceptable images) Operating temperature, optimal (Camera produces optimal optical performance) Digital power supplies operating range (@ module pin(1)) Analog power supplies operating range (@ module pin(1)) Min. -30 -25 5 1.7 2.4 2.4 Max. 70 55 30 2.0 3.0 3.0 Unit C C C V V V
1. Module can contain routing resistance up to 5 .
58/70
VL6524/VS6524
Electrical characteristics
13.3
Note:
Table 34.
Symbol VIL
DC electrical characteristics
Over operating conditions unless otherwise specified.
DC electrical characteristics
Description Input low voltage Test conditions VDD 1.7 ~ 2.0 V VDD 2.4 ~ 3.0 V Input high voltage VDD < 2.7 V VDD > 2.7 V Output low voltage Output high voltage IOL < 2 mA IOL < 4 mA IOL < 4 mA 0.8 VDD -10 -1 -2 +10 +1 Min. -0.3 -0.3 0.7 VDD 0.7 VDD Typ. Max. 0.25 VDD 0.3 VDD VDD + 0.3 3.46 0.2 VDD 0.4 VDD V V V V A A A pF pF pF Unit V
VIH VOL VOH
IIL
Input leakage current Input pins 0 < VIN < VDD I/O pins Input leakage current SDA and SCL pins VIH > VDD + 0.3V
+500 6 6 8
CIN COUT CI/O
Input capacitance, SCL Output capacitance I/O capacitance, SDA
TA = 25 C, freq = 1 MHz TA = 25 C, freq = 1 MHz TA = 25 C, freq = 1 MHz
Table 35.
Symbol
Typical current consumption
IVDD Description Supply current in power down mode Supply current in Standby mode Supply current in Stop mode Supply current in Pause mode Supply current in active streaming run mode Test conditions IAVDD VDD = 1.8V VDD = 2.8V Units
IPD Istanby Istop IPause Irun
CE=0, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz streaming VGA @30 fps
0.01 0.001 0.002 0.050 8.3
0.6 0.4 0.4 14.99 32.6
0.8 1.2 7.45 24.4 41.0
A mA mA mA mA
59/70
Electrical characteristics
VL6524/VS6524
13.4
13.4.1
AC electrical characteristics
External clock
The VL6524/VS6524 requires an external clock. This clock is a CMOS digital input. The clock input is fail-safe in power down mode. Table 36. External clock
Range CLK Min. DC coupled square wave Clock frequency (normal operation) 6.50 Typ. VDD 6.50, 8.40, 9.60, 9.72, 12.00, 13.00, 16.80, 19.20, 19.44 26 Max. V MHz Unit
13.4.2
Chip enable
CE is a CMOS digital input. The module is powered down when a logic 0 is applied to CE. See Chapter 4 for power down and for power-up sequence.
13.4.3
IC slave interface
VL6524/VS6524 contains an IC-type interface using two signals: a bidirectional serial data line (SDA) and an input-only serial clock line (SCL). See Chapter 10 for detailed description of protocol. Table 37.
Symbol
Serial interface voltage levels(1)
Standard Mode Parameter Min. Max. Min. Max. Hysteresis of Schmitt Trigger Inputs VDD > 2 V VDD < 2V LOW level output voltage (open drain) at 3mA sink current N/A N/A N/A N/A 0.05 VDD 0.1 VDD V V Fast Mode Unit
VHYS
VOL1 VOL3 VOH tOF
VDD > 2 V VDD < 2V HIGH level output voltage Output fall time from VIHmin to VILmax with a bus capacitance from 10 pF to 400 pF Pulse width of spikes which must be suppressed by the input filter
0 N/A N/A -
0.4 N/A N/A 250
0 0 0.8 VDD 20+0.1Cb(2)
0.4 0.2 VDD
V V V
250
ns
tSP
N/A
N/A
0
50
ns
1. Maximum VIH = VDDmax + 0.5 V 2. Cb = capacitance of one bus line in pF
60/70
VL6524/VS6524 Figure 32. Voltage level specification
Input voltage levels
Electrical characteristics
Output voltage levels
VOH = 0.8 * VDD VIH
VIL VOL = 0.2 * VDD
Table 38.
Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb VnL
Timing specification(1)
Standard mode Parameter Min. SCL clock frequency Hold time for a repeated start LOW period of SCL HIGH period of SCL Set-up time for a repeated start Data hold time (1) Data Set-up time (1) Rise time of SCL, SDA Fall time of SCL, SDA Set-up time for a stop Bus free time between a stop and a start Capacitive Load for each bus line Noise Margin at the LOW level for each connected device (including hysteresis) Noise Margin at the HIGH level for each connected device (including hysteresis) 0 4.0 4.7 4.0 4.7 300 250 4.0 4.7 0.1 VDD Max. 100 1000 300 400 Min. 0 0.6 1.3 0.6 0.6 300 100 20+0.1Cb(2) 20+0.1Cb(2) 0.6 1.3 0.1 VDD Max. 400 300 300 400 kHz s s s s ns ns ns ns s s pF V Fast mode Unit
VnH
0.2 VDD
-
0.2 VDD
-
V
1. All values are referred to a VIHmin = 0.9 VDD and VILmax = 0.1 VDD 2. Cb = capacitance of one bus line in pF
61/70
Electrical characteristics Figure 33. Timing specification
SDA
VL6524/VS6524
tSP tSU;STA SCL tHD;STA tHD;DAT tSU;DAT tSU;STO tBUF tHD;STA
S START
tLOW
tHIGH
tr
tf
P STOP
S START
All values are referred to a VIHmin = 0.9 VDD and VILmax = 0.1 VDD
Figure 34. SDA/SCL rise and fall times
0.9 * VDD 0.9 * VDD
0.1 * VDD
0.1 * VDD
tr
tf
62/70
VL6524/VS6524
Electrical characteristics
13.4.4
Parallel data interface timing
VL6524/VS6524 contains a parallel data output port (D[7:0]) and associated qualification signals (HSYNC, VSYNC, PCLK and FSO). This port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or bit-serial output configurations. The port is disabled (high impedance) upon reset. Figure 35. Parallel data output video timing
1/fPCLK tPCLKL PCLK polarity = 0 tDV D[0:7] HSYNC VSYNC Valid tPCLKH
Table 39.
Symbol fPCLK tPCLKL tPCLKH tDV
Parallel data interface timings
Description PCLK frequency PCLK low width PCLK high width PCLK to output valid 10 10 -5 5 Conditions Min. Typ. Max. 26 Unit MHz ns ns ns
13.5
ESD handling characteristics
Table 40. ESD handling characteristics
Test ESD Machine Model ESD Human body Criteria 150 1.5 Unit V kV
63/70
Package outline
VL6524/VS6524
14
14.1
Package outline
SmOP
Packing Dimension
Figure 36. VS6524Q06J outline drawing
Optical Lens Specification: Focusing Range 20 cm to Infinity Focal Length 2.53mm F Number F2.8 Fov(D) 60.8 TV Distortion < 1%
Pin No.
1 2 3 4 5 6 7 8 9 10
RECESS 0.1max
1.200.05
CAVITY NO. PROTRUDE 0.05max
8-
R0
TOP VIEW
.5
.00 O5 0 .9 O5
0.500.05 6.00
0
Name
GND DO2 DO3 HSYNC VSYNC DO7 DO6 DO5 DO4 CLK 1
Pin No.
11 12 13 14 15 16 17 18 19 20
Name
GND FSO 1 CE 1 SCL 1 SDA AVDD(2.8V) DO1 DO0 PCLK VDD(1.8V) 1
2
protrude 0.05max
Pin1 mark
A
6.00
SIDE VIEW
TOOL NO. PROTRUDE 0.05max
BOTTOM VIEW
1.800.05 2 1.050.05 2 0.50
4-
O
0.
5.000.05 2.60
60
1.450.05 2
0.700.05
20 1
2
5.000.05 0.500.05
2
3
3.35 1 3.300.15 4.350.15
Pin1 mark
4
0.400.05 2 0.3250.05 0.650.05
Note:# Image direction register use default settings. Socket:ALPS P/N:SCKA2A0100 Socket Cover:ALPS P/N:JSCKA0002A
Basic Tolerance 0.10mm
64/70
VL6524/VS6524 Figure 37. VS6524Q06J socket assembly outline drawing for information only
TOP VIEW
Package outline
BOTTOM VIEW
7.40 6.20
A
A
1.75
A-A SECTION
A
Socket Cover Holder
Socket PCB
3.85 3.45
3
CMOS Sensor
3.35 4.350.15 4 5.200.30
IR 4
Note:# Image direction register use default settings. Socket:ALPS P/N:SCKA2A0100 Socket Cover:ALPS P/N:JSCKA0002A
6.20 7.40
Lens Camera Protection
Basic Tolerance 0.10mm
65/70
Package outline
VL6524/VS6524
14.2
LGA
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 41. LGA package mechanical data
Data book (mm) Symbol A A4 A5 B1 B2 B3 b D D1 D2 D4 e E E1 E2 E4 G G1 G2 G3 G4 H H1 H2 I J K 0.3 3.95 0.8 0.3 0.8 1.0 9.90 9.60 0.25 9.90 9.60 Min. 1.80 0.35 0.7 Typ. 1.90 0.4 0.8 2.0 3.5 0.55 0.30 10.00 9.70 5 5.4 0.8 10.00 9.70 5 4.5 1.1 1 0.4 0.9 0.8 0.9 0.8 0.4 4.05 4.1 0.3 0.5 4.15 1.0 0.5 1.0 1.2 10.10 9.80 0.35 10.10 9.80 Max. 2.00 0.45 0.9
66/70
VL6524/VS6524 Table 41. LGA package mechanical data (continued)
Data book (mm) Symbol PHI z L bbb ccc ddd eee nD nE n 0.7 Min. 4 Typ. 5 1.65 0.8 0.01 0.1 0.08 0.08 9 9 36
Package outline
Max. 6
0.9
67/70
Package outline Figure 38. VL6524QOMH outline drawing
VL6524/VS6524
68/70
VL6524/VS6524 Table 42.
Pin 1 2 3 4 5 6 7 8 9
Ordering information VL6524 pin assignment
Signal AVDD GND SDA SCL CE VDD CLK GND FSO Pin 10 11 12 13 14 15 16 17 18 Signal GND NC NC NC NC AVDD HSYNC VSYNC GND Pin 19 20 21 22 23 24 25 26 27 Signal DIO7 DIO6 DIO5 DIO4 VDD DIO3 DIO2 DIO1 DIO0 Pin 28 29 30 31 32 33 34 35 36 Signal GND PCLK VDD NC NC NC NC NC GND
15
Ordering information
Table 43. Order codes
Part number VS6524Q06J VL6524QOMH IMG-524-E01 IMG-524-P02 SmOP 6x6x4.35 mm LGA 10x10x1.90 mm Baseboard with socket plug-in for X24 camera integration kit LGA package plug-in for X24 camera integration kit Package
16
Revision history
Table 44.
Date 21-Mar-2006
Document revision history
Revision 1 Initial release. Updates in Table 30: Optical specifications and addition of Section 12.1: Average sensitivity and Section 12.2: Spectral response. Updates in Table 34: DC electrical characteristics Updates in Table 40: ESD handling characteristics Updates in Figure 35: Parallel data output video timing Addition of VL6524 reference and package outline drawing. Changes
29-Jun-2006
2
06-Nov-2006
3
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VL6524/VS6524
Please Read Carefully:
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